4 Replies Latest reply on Nov 20, 2019 7:48 AM by tarribred61

    Polygon pour issue/bug



      I have been battling with a bug related to using the “Polygon pour” functionality for some time to no avail. The issue(s)/bug(s) is/are described below:


      The board has four (4) layers, which are labeled as Top, L1, L2, and Bottom. All layers have been declared/assigned as “signal layer” except L1 which has been declared as an “internal plane” layer. Moreover, the board has a square shape with rounded corners.


      Issue 1: When I try to carry out a polygon pour operation on the Top or Bottom layer, the filling algorithm/routine fills the entire (square) selected area. That is, it does not remove the dead copper which is outside the rounded corner area. Note that the check for removing the dead copper is enabled. But, the polygon pour operation works perfectly on the L1 layer which has been defined as an internal plane layer.


      I have tried an alternative approach by defining the shape of the board on the Mechanical Layer, and then selecting the shape to do a “Define from selected objects”. This does not work properly either.


      Issue 2: The L2 layer contains micro-vias that go from the L2 layer to the Bottom layer. Also, there are some through-vias that go from the Top layer to the Bottom layer. When I try to carry out a polygon pour operation on the L2 layer, the filling algorithm connects the poured section to the through-vias that do not belong to the same (selected net, i.e. GND net). But, the filling algorithm works as expected for all other regions including the micro-vias. It is as if the filling algorithm/routine has an issue with those items (through-vias) that don’t start/finish on this layer.


      Any suggestions?






        • Re: Polygon pour issue/bug

          Hey Mo,


          For number 1: I think Altium Designer works this way too and it is not a bug.  To get your layers to pour properly you either need to shape the areas exactly the way you want (not ideal) or use rules (this is preferred).  Maybe try what I describe below and see if it helps.


          Open Design Rules > Electrical > Clearance and make a new rule called Clearance_PolyTopLayer


          Set the first object match to layer and top layer.  Set the second object match to layer and Keep-Out Layer.


          If your keep-out layer is defined as the board outline with a thicker line such as 1mm then the top layer pour should pull back from the board edge by 0.5mm (1/2 the line width).  If the box for remove dead copper is checked then it should trim off the unconnected outer portions.  So basically you can put a big rectangular pour on the top layer that overhangs the PCB and it should trim off the off board copper and include a pull-back from the edge.


          I'm not sure about your #2 issue as I have not used blind vias with CircuitStudio.

          Screen shots for you:

          1st: here is top copper pour (red) and keepout (pink).  This PCB is unrouted as I'm in placement right now.


          Here is single layer mode showing keepout and then copper only

          Here is my rule.  Full AD has more powerful rules but the process is basically the same.

          Or you could instead define the rule to apply to polygons.


          I confess to not being an expert at this (yet) though so some experimentation on your part is needed and maybe someone else can post a response.


          This link seems to describe some of the idea but with AD so it isn't exactly applicable.



          • Re: Polygon pour issue/bug

            Perfect answer! it works exactly as described.


            As for Issue 2, the software works fine with the micro-vias. The problem is related to through-vias, where the polygon fill works as expected on the Top and Bottom Layers, but not an inner layer, unless that inner layer is declared as an "Internal plane".


            Any solutions regarding issues 2 is most appreciated.