4 Replies Latest reply on Feb 14, 2020 10:12 AM by wwqiao

    How to understand the swapped pins of UART0/1 on Avnet CC?




      According to Xilinx TRM document, UART0 uses MIO_34 (TX) and MIO_35 (RX), and UART1 uses MIO_32 (RX) and MIO_33 (TX).


      On the Avenet Carrier Card, UART0's TX MIO_34 is connected to U16 CP2105's TXD_SCI and RX MIO_33 to U16's RXD_SCI. UART1's TX/RX pins are also swapped.


      How to understand this design?