4 Replies Latest reply on Oct 5, 2020 12:19 PM by mbrown

    How to use the AES_LPA_502_G board




      We purchased ZCU111 Xilinx FPGA evaluation board with its daughterboard (XM500). We sent a tone through XM500 to the ZCU111 and saw the spectrum on the RF GUI provided by Xilinx. Later we purchased two AES-LPA-502-G daughter board from Avnet. Then replaced the XM500 with AES-LPA-502-G. We didn't observed any signal on the Xilinx RF GUI. We were wondering what is missing? Thanks


        • Re: How to use the AES_LPA_502_G board

          Hi Ali,


          My first thought is that you are experiencing DC offset.


          The XM502 implements baluns on 4 channels with Pi pad attenuators, which provides a few things:

          1. Single-ended to differential
          2. AC coupling
          3. Improves return loss

          Source: https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf


          The Avnet LPA-502 card makes all 8x8 channels available fully differential, with no baluns, attenuation networks, or AC coupling. It's up to you to provide DC blocking inline.


          Did you insert DC blockers in your XM502 connection?



            • Re: How to use the AES_LPA_502_G board

              Another consideration when using the XM502 is DC biasing the ADC and DAC paths.


              See “AC/DC Coupling Guidelines” of Xilinx UG583 - UltraScale Architecture PCB Design (v1.19)


              Specifically, table 3-2

                • Re: How to use the AES_LPA_502_G board

                  Regarding signal swing into the ADC:


                  The LPA-502 is completely passive – no baluns, amplifiers, or attenuators. Depending on frequency, you can estimate ~0.5 dB of loss through each connector. With that in mind, consulting Xilinx DS926 would be the most prudent guidance for determining max signal swing into the LPA-502.


                  For example, with RFSoC Gen1 devices, Xilinx DS926 specifies full-scale input to the ADC at 1Vpp into 100ohms (internal termination), which corresponds to ~ 1dBm. Presenting this signal at the input of the LPA-502 SMA connector will ensure that you are safely driving the pins of the RFSoC device. In order to get close to full-scale at the RFSoC pins, you could consult the LPA-502 HW User’s Guide. Page 14 includes insertion loss simulations based on s-parameters of the card. From those curves you could estimate the additional signal power required to arrive at the RFSoC pins at 1 dBm.

                    • Re: How to use the AES_LPA_502_G board

                      Regarding the RF-DAC output swing...


                      The DAC is a current mode output, so a full-scale digital input will produce the largest voltage swing for a given load.


                      Using the Xilinx RFSoCRF-DAC Electrical Characteristics for ZU2xDR Devices, and the assumption that we’re driving into 100 ohms differential:


                      • AvgPwrWatts = Vrms^2/Rload
                      • Pdbm = 10*log10(AvgPwrWatts/0.001)




                      • 20mA mode,  signal swing would be ~1Vpp to achieve +1dBm into 100ohms.
                      • 32mA mode,  signal swing would be ~1.6Vpp to achieve +5dBm into 100ohms.


                      Since the LPA-502 connectors and PCB traces present some non-zero resistance, the numbers above will be lower in practice.