4 Replies Latest reply on Mar 24, 2020 4:01 PM by msdh

    Constraints and bitstream generation

    msdh

      I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board and familiar with Verilog modules/test bench as beginner. I am using Vivado 2018.2

      I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button).

      Inside my top module I've three modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000.

      Here is my constraint file:

      # Clock Source - Bank 13
      set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK"
      # ----------------------------------------------------------------------------
      # User LEDs - Bank 33
      set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0"
      set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1"
      set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2"
      set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3"
      set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4"
      set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5"
      set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6"
      set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7"

      # User Push Buttons - Bank 34
      # ----------------------------------------------------------------------------
      set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC"
      set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND"

      # ----------------------------------------------------------------------------
      # User DIP Switches - Bank 35
      # ---------------------------------------------------------------------------
      set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0"
      #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
      # ---------------------------------------------------------------------------
      # IOSTANDARD Constraints
      # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
      set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
      # Set the bank voltage for IO Bank 34 to 1.8V by default.
      set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
      # Set the bank voltage for IO Bank 35 to 1.8V by default.
      set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
      # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
      set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
      set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF];

      My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create a constraint file for each of them.

      The error I got:

      Please help me to understand and solve the issue.

        • Re: Constraints and bitstream generation
          drozwood90

          Hi there,

           

          From the sparse information you provided, looks like you might have chosen the wrong part.  Make sure you are using the Zynq 7020.  Better to use a BDF, which would set everything up for you.  I'm not sure if Digilent has a BDF or not.  You'll have to check their support site.

           

          Lastly, you'll probably want to ask this over at the Digilent forum:

          https://forum.digilentinc.com/

           

          --Dan

            • Re: Constraints and bitstream generation
              msdh

              Hi Daniel, thanks for respond.

              I did check the right part number and it matches my board. I am using xc7z020clg484-1 or ****-2 getting the same result.

              I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program".

              This part number was used in another simpler project contained only one module and constraint file, it was working fine with no error generating Bitstream or programming my device. As soon as I modified my program to have a top-module with three sub modules in it the errors came up.

              Please refer to the screenshots and let me know if I am not clear enough.