I have just run a DRC check on a board I am working on. The board has an MSP432 TI processor on it with a 128 pin SMD package. The pads are .008" X.055" and they are on a .01575" pitch. This leaves .00775" between each pad. I run DRC with a .006" minimum clearance and DRC gives me a clearance error between every pad. I appear to be missing something as it looks like I have more then .006" between each pad.
Any ideas why DRC is flagging errors. The MSP432E401YTPDT is in a 128-TQFP. The package appears to be correct. Its simple math.
I figured it out, The Device had all its nets under a net Class of 0. Net Classes have clearances that DRC uses over the ones listed in the DRC tab. Eagle (Ver 7) doesn't tell you anything but "Clearance Error". I used a board design that some one else did and added to that design. The previous designer specified Net Classes with an 8mil clearance limit so all nets with a 0 Net class had .008 not .006 limits. I altered the one parameter and 500 errors went away.