7 Replies Latest reply on Jul 1, 2020 1:56 PM by bhfletcher

    Ultra96-V2 Vivado 2019.2 IOPLL error wrong divider


      Hi there,


      I'm new to Xilinx and Ultra96-v2 boards.

      I've been trying to create hardware descripion in Vivado and went to error situation.

      There is wrong IOPLL divider set.

      When I change it to 91 (including enable of divider 2) then I have following error:

      [BD 41-1273] Error running post_config_ip TCL procedure: unexpected "," outside function argument list

          ::xilinx.com_ip_zynq_ultra_ps_e_3.3::post_config_ip Line 47"


      Besides that I see a number of: "[IP_Flow 19-2373] Cannot identify default part." errors.


      Can you help me with those?