1 Reply Latest reply on Jul 2, 2020 11:20 AM by Autodesk Guest

    IC Design Across Hierarchical Blocks

    jleazott

      I am trying to make an 8 bit ALU in Eagle but I am running into a huge problem. I am using Eagle's module system to create an individual adder, then another to create a bit slice, lastly a few schematics to add all the extra components.

       

      Here is the problem, each hierarchical block is purely independent of one another.

      So each adder contains 2 XOR, 2 AND, and 1 OR gate. Since I am using the 74LS series (particularly the quad 2 input sets) I am only using half of the XOR, half the AND, and a quarter of the OR chip.

      If I were to then place 2 adder modules in a schematic I would have 4 XOR, 4 AND, and 2 OR gates which works and ideally I would only use 3 IC's.

      However, I instead end up with 6 because each adder instance uses 3.

      I know with OrCAD this is fixed by Annotating and works really well and know there has to be something like this in Eagle.

      I have tried using Eagles renumber parts but that does nothing for my situation.

       

      I know I could use design blocks but I would prefer to keep the abstraction of no longer seeing what is inside the slice and also having it all update nicely when I change the module

       

      Thanks

        • Re: IC Design Across Hierarchical Blocks
          Autodesk Guest

          Jacob Leazott wrote:

           

          I am trying to make an 8 bit ALU in Eagle but I am running into a huge problem. I am using Eagle's module system to create an individual adder, then another to create a bit slice, lastly a few schematics to add all the extra components.

           

          Here is the problem, each hierarchical block is purely independent of one another.

          So each adder contains 2 XOR, 2 AND, and 1 OR gate. Since I am using the 74LS series (particularly the quad 2 input sets) I am only using half of the XOR, half the AND, and a quarter of the OR chip.

          If I were to then place 2 adder modules in a schematic I would have 4 XOR, 4 AND, and 2 OR gates which works and ideally I would only use 3 IC's.

          However, I instead end up with 6 because each adder instance uses 3.

          I know with OrCAD this is fixed by Annotating and works really well and know there has to be something like this in Eagle.

          I have tried using Eagles renumber parts but that does nothing for my situation.

           

          I know I could use design blocks but I would prefer to keep the abstraction of no longer seeing what is inside the slice and also having it all update nicely when I change the module

           

          Thanks

           

          Have you considered using 74..1G.. 74..2G.. ?

          May even make the layout easier.

          --

           

          Lorenz