9 Replies Latest reply on Jul 24, 2020 12:53 PM by kah5236

    using the FPGA on the Ultra96-V2

    kah5236

      Hi,

        I’ve been successful doing hello world, playing with sensors and using PYNQ and now I’m trying to do a simple LED blinky using ONLY the FPGA part of the ULTRA-96-V2 using Verilog. I want drive an LED(s)  totally off board since that is closer to the next project I’m planning.  I was also going to take advantage of some voltage shifters on a Linaro/Grove Sensors Adapter card before getting to the LED on a protoboard.  When I try to do FPGA pin assignments in Vivado, the pins I want to assign apparently aren’t valid and comes back with “Invalid placement site” with mouse hovering. I traced the schematics of both the sensor card and Ulta96v2 card thru the expansion connection to GPIO pins off the FPGA so I don’t get why I can’t assign pins like FPGA pins A11 or B11 (MIO44_PS_GPIO_4 and MIO045_PS_GPIO_5) in Vivado.

      I also pivoted and tried to just use the ULTA96-V2 user LEDs and traced those to FPGA pins AB4 and AA4 and those pins also are not valid to use. I would have thought any pins that go to the expansion connector(s) on the cards would be available to use but it doesn’t look that way.

      I’m probably missing something simple. I’m assuming the support package (BSP)  for ULTRA96-V2 card puts the constraints on but I'm just not sure .

       

      Anyone have any guidance?

        • Re: using the FPGA on the Ultra96-V2
          bhfletcher

          Only PL I/O pins are constrained with pin assignments in a constraints file. The PS MIO pins are assigned as part of the Block Design, which becomes your FSBL.

           

          The LS Expansion contains both PL I/O and PS MIO pins, so it depends on which ones you target. For example, any of these Bank 26 pins are eligible PL I/Os connected to the LS Expansion.

           

          Bryan

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          • Re: using the FPGA on the Ultra96-V2
            narrucmot

            Hi Kurt,

             

            Are you looking to add your Verilog to blink an LED on the Ultra96-V2 to an existing Vivado design, or are you starting from scratch?

             

            If starting from scratch you will be able to use LED D9 and D10 as GPIO LEDs.  These are normally used by Linux to signal that the WiFi & BlueTooth interfaces are active.  These are mapped to PL I/O pins:

             

            #######################################################################
            # Ultra96 WiFi & BT LEDs
            #######################################################################
            set_property IOSTANDARD LVCMOS18 [get_ports *_en_led*]
            
            
            #RADIO_LED0 on FPGA / LED D9 / WiFi LED
            set_property PACKAGE_PIN A9 [get_ports {wifi_en_led_tri_o[0]}]
            #RADIO_LED1 on FPGA / LED D10 / Bluetooth LED
            set_property PACKAGE_PIN B9 [get_ports {bt_en_led_tri_o[0]}]
            

             

            The ZU+ device pins A6 and C7 are mapped to the the LS mezzanine connector HD_GPIO_6 and HD_GPIO_13 and are normally mapped to the PWM IPs in the PL:

            #######################################################################
            # Ultra96 LS Mezzanine PWMs
            #######################################################################
            # These constraints are used for when connecting the LS Mezzanine PWM to 
            # the PWM_w_Int custom IP block.
            set_property IOSTANDARD LVCMOS18 [get_ports ls_mezz_pwm*]
            
            
            #HD_GPIO_6 on FPGA / Connector pin 29 / PWM1
            set_property PACKAGE_PIN A6 [get_ports {ls_mezz_pwm0[0]}]
            #HD_GPIO_13 on FPGA / Connector pin 30 / PWM2
            set_property PACKAGE_PIN C7 [get_ports {ls_mezz_pwm1[0]}]
            

             

            If you are trying to add your blinky LED logic to an existing design - perhaps the Vivado design used for the Ultra96-V2 PetaLinux BSP - then I believe all the LEDs mapped to PL I/Os will have already been constrained for use by other peripherals.  It may take some careful mapping to determine what PL I/Os are available for use on the LS mezzanine connector and make sure they aren't already constrained for use by peripherals already in the Vivado design (UARTs, etc.).

             

            --Tom

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              • Re: using the FPGA on the Ultra96-V2
                kah5236

                Thanks Tom,

                I'm trying to do the blinky from scratch.  Based on the responses  from you and Bryan, the scope of usable GPIO pins seems limited and roughly  matches  the pulldown menu list of pins I see in Vivado.  (I haven't done a line by line check yet).  That's leading me to understand there are indeed limitations. beyond what I see from just  looking at the board(s) schematic but I don't  understand the reason  why.  I can guess many pins are saved for some sort of peripherals but not on the Ultra96 card itself based on the schematic. So am I correct the Ultra96-v2 BSP file is most likely the source of the limitation rather than some Vivadao switch or an FPGA IO bank rule I've missed?

                 

                Kurt H.

                  • Re: using the FPGA on the Ultra96-V2
                    sjindal

                    Hi Guys,

                     

                    Ttoday, I have joined this forum and I came across verilog / VHDL / FPGA ( my old passion )

                     

                    please let me know if I can join in any project . Happy to share further detail.

                     

                    thanks

                    sushil

                    • Re: using the FPGA on the Ultra96-V2
                      narrucmot

                      Compared to other Zynq UltraScale+ devices the ZU3EG in the SBVA484 package on the Ultra96-V2 board is more I/O bound than most.  Further, the Linaro 96boards "Consumer Edition" specification (https://linaro.co/ce-specification) that the Ultra96 board complies with specifies what interfaces are expected, and where they are expected, on the Ultra96 board and on the low-speed and high-speed mezzanine connectors.  This further constrains the number of available I/Os for GPIO use.  Many of these interfaces - 3 x USB, uSD card, WiFi (SD), Bluetooth (UART), UARTs, SPI, and I2C are also connected directly to the ZU+ Processing System.

                        • Re: using the FPGA on the Ultra96-V2
                          kah5236

                          I was able to blink my external LEDs by using the GPIO K & L signals off connector G5 on the Linaro/Grove  mezzanine card which translated  to pins G6 and C5 on the FPGA.   As mentioned, the GPIOs are pretty limited, only a handful were available I could use that were truly general purpose.  Though successful, I still don’t understand where the available pins in the pulldown menu in Vivado gets defined.    To satisfy my curiosity, I ended up just writing down all the pins that the pulldown menu had available, there were 82 of them.   For my tiny little project I traced the signals back from the Grove mezzanine card that were both on voltage translators and the LS expansion connector thru the Ultar96V2 card’s expansion connector back to the FPGA that aided my success.

                          I also started to trace many of the pins that were in the Vivado pull down menu through the Ultra96 card and that  set of pins  went everywhere, some were GPIO signals  but many were dedicated functions and even a clock or two. Just picking a pin at random off that menu would not be good.   That convinced me that the pins on that pulldown  menu  are NOT coming from an Ultra96 board definition file, I just don’t know where the list come from since I think some are missing and others shouldn’t be there for an Ultra96 application. 

                            • Re: using the FPGA on the Ultra96-V2
                              bhfletcher

                              I suspect that Vivado gives you access to every possible I/O on the selected package, regardless of whether they are connected or not connected, whether they are general-purpose or dedicated on a particular board. You are correct that Vivado is not getting the pins in that pull-down from the Ultra96-V2 board definition.

                               

                              Between PL banks 26, 65, and 66, The Ultra96-V2 connects 53 of them, and 29 of them are No-Connects. As you can see, 53 + 29 = 82 is the total number of PL I/Os on the particular ZU+ device/package that we have on the Ultra96-V2. Vivado does not have enough board awareness to know whether they were connected or not.

                               

                              Bryan

                      • Re: using the FPGA on the Ultra96-V2
                        kah5236

                        To close out the discussion and help others that might have similar questions, part of my initial confusion also came because I failed to pay close attention to the PL vs PS division of pins, PS pins would not be available to the PL part of the device.