I have a working U96v1 design that I ported over to U96v2. Everything seems to be working in the new v2 design, Vitis DPU integration, Xilinx drivers including DRM all boot up OK, our HW and drivers in linux all work, etc. We are using standard 2019.2 flow: Vivado-PLNX-Vitis.
However, the display port display won't come up, i.e. when I run the basic test:
modetest -M xlnx -s 39:1920x1080@RG16
it runs OK, but no colorbar display (no HDMI signal). Note I am using same display, cable, drivers, SW environment on U96V1 and it works perfectly.
Also if I run X :0 and a test app like xclock it does not come up.
I have checked kernel config likes CMA memory, the xlnx-drm messages in dmesg, the card0-DP-1 is connected and working (see modetest results below). The drm driver seems to be booting just fine (exactly the same dmesg as V1).
I did suspect something with the i2c interface, but i2cdetect -l shows proper ZynqMP DP AUX coming up on i2c-1, and if I read EDID with display plugged in, it matches what I see in the V1. However, in all the testing I've done, I did see an EDID error once or twice, but that may have been just from plugging/unplugging the cable. Also I do see an i2c config error in dmesg that is not in the u9v1 log, but I think that does not affect DisplayPort (see below).
Any ideas what to check? The only thesis I can think of is:
1. maybe the i2c write to the display is not working - does the driver ever make i2c writes to the display?
2. there is an dp_oe (display port output enable signal) driven by MIO29. Could that be inverted or messed up somehow, i.e in the device tree or somewhere in the driver config?
3. maybe other issues with devicetree? There are some difference between v1 and v2, but they all seem to be in the system-user.dtsi and unrelated to DisplayPort.
So its much appreciated if Avnet expert could comment on above, that is:
1. review devicetree for problems - I attach system-user.dtsi which is from Petalinx with some additions for our HW. Note the zxyclmm entry is manual for the DPU entry, following the VitisAI instructions for U96.
2. instruct how to check the MIO29-dp_oe operation is working correctly, config/constraints are correct, etc.
3. advise if i2c write to ZynqMP_DP_AUX could be a problem and how to check it.
Many thanks - any further advice is appreciated.