5 Replies Latest reply on Jan 6, 2021 11:05 AM by bhfletcher

    Petalinux 2020 BSP for the Ultra96-v2 development board

    htekosin

      Anyone seen the Petalinux 2020 Board Support Package for the Zync UltraScale+ 96 MPSoC v2 development board ?

        • Re: Petalinux 2020 BSP for the Ultra96-v2 development board
          narrucmot

          This PetaLinux 2020.1 BSP for the Ultra96-V2, as well as others for the UltraZed and Zed SOMs and SBCs, have been submitted for posting online, but that sometimes takes a long time.  In the meantime it can be downloaded from here (this link expires on 11/30/2020):

          https://avtinc.sharepoint.com/:u:/t/ET-Downloads/ERMhK82z4ZpPpu-1IP3EkiYBrjriOf026byKaNJmW6dAhQ?e=XCL4z1

           

          --Tom

          2 of 2 people found this helpful
            • Re: Petalinux 2020 BSP for the Ultra96-v2 development board
              htekosin

              Great! I am downloading it now and will go through the whole petalinux thing with it and report any issues I find.

              Thanks very much for the help Tom!

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                • Re: Petalinux 2020 BSP for the Ultra96-v2 development board
                  htekosin

                  hmmm... it seems to have gone a little further this time. I put BSCAN-JTAG hardware, a debug_bridge device-tree entry and an xvcserver.c app in there. Still crashing after the AMBA setup though.

                   

                  I can see from the early UART output that it has loaded the device-tree. However, I cannot see anything indicating that it has written the bitstream or configured the PL or PS at all. I assume this means that the kernel panic is not caused by the Vivado generated bitstream I have indicated on the petalinux-package command with the --fpga switch. However, I see form the XSA sysdef.xml that the psu_init.c PS setup C code is labelled PS_FSBL_INIT which implies to me that it is actually part of the FSBL. That makes sense to me now as of course the system will want to do this early on say, for example, to provide infrastructure for the XVC. However, as my previous post shows, the systems halts even without any psu_init.c or bitstream. Clearly I have no idea what I am doing. Again I have read 2 books so far and am reading the Documentation in the tool that Xilinx provides. I hope 1 day to know what I am doing although it might take all the fun out of it.

                   

                   

                  ...
                  [    0.000000] irq-xilinx: /amba/axi-interrupt-ctrl: num_irq=32, sw_irq=0, edge=0x0 [    0.000000] SError Interrupt on CPU0, code 0xbf000000 -- SError [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.0-xilinx-v2020.1 #1 [    0.000000] Hardware name: Avnet Ultra96 Rev1 (DT) [    0.000000] pstate: 60000085 (nZCv daIf -PAN -UAO) [    0.000000] pc : xintc_read.isra.0+0x0/0x48 [    0.000000] lr : xil_intc_initial_setup+0x48/0x110 [    0.000000] sp : ffffffc011063e30 [    0.000000] x29: ffffffc011063e30 x28: 0000000000fb0018 [    0.000000] x27: ffffffc011063f08 x26: dead000000000100 [    0.000000] x25: dead000000000122 x24: 0000000000000008 [    0.000000] x23: ffffff805fad9088 x22: ffffffc011072f80 [    0.000000] x21: ffffff805faf44f8 x20: 0000000000000000 [    0.000000] x19: ffffff803ee47700 x18: 0000000000000010 [    0.000000] x17: ffffff803ee41088 x16: ffffff803ee410a8 [    0.000000] x15: ffffffc0110733a8 x14: 0000000000000000 [    0.000000] x13: 0000000000000280 x12: 0000000000000000 [    0.000000] x11: 0000000000000001 x10: 0000000000000040 [    0.000000] x9 : ffffffc01107cd50 x8 : ffffffc01107cd48 [    0.000000] x7 : ffffff805d000278 x6 : 0000000000000001 [    0.000000] x5 : 0000000000000000 x4 : ffffff803ee4b8a4 [    0.000000] x3 : 0000000000000000 x2 : 0000000000000003 [    0.000000] x1 : 000000000000001c x0 : ffffffc010005000 [    0.000000] Kernel panic - not syncing: Asynchronous SError Interrupt [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.0-xilinx-v2020.1 #1 [    0.000000] Hardware name: Avnet Ultra96 Rev1 (DT) [    0.000000] Call trace: [    0.000000]  dump_backtrace+0x0/0x140 [    0.000000]  show_stack+0x14/0x20 [    0.000000]  dump_stack+0xac/0xd0 [    0.000000]  panic+0x140/0x2f8 [    0.000000]  __stack_chk_fail+0x0/0x18 [    0.000000]  arm64_serror_panic+0x74/0x80 [    0.000000]  do_serror+0x114/0x118 [    0.000000]  el1_error+0x84/0xf8 [    0.000000]  xintc_read.isra.0+0x0/0x48 [    0.000000]  xilinx_intc_of_init+0x258/0x30c [    0.000000]  of_irq_init+0x184/0x2e4 [    0.000000]  irqchip_init+0x14/0x1c [    0.000000]  init_IRQ+0xe8/0x118 [    0.000000]  start_kernel+0x26c/0x42c

                  Thanks

                  Let me know if I should include any other logs or system details.

                  • Re: Petalinux 2020 BSP for the Ultra96-v2 development board
                    htekosin

                    I have also added the following in to the system-conf.dtsi but still get the same problem:

                    &amba {
                         zyxclmm_drm {
                              compatible = "xlnx,zocl";
                              status = "okay";
                              interrupt-parent = <&axi_intc_0>;
                              interrupts = <0  4>, <1  4>, <2  4>, <3  4>,
                                        <4  4>, <5  4>, <6  4>, <7  4>,
                                        <8  4>, <9  4>, <10 4>, <11 4>,
                                        <12 4>, <13 4>, <14 4>, <15 4>,
                                        <16 4>, <17 4>, <18 4>, <19 4>,
                                        <20 4>, <21 4>, <22 4>, <23 4>,
                                        <24 4>, <25 4>, <26 4>, <27 4>,
                                        <28 4>, <29 4>, <30 4>, <31 4>;
                         };
                    };
                    
                    &axi_intc_0 {
                          xlnx,kind-of-intr = <0x0>;
                          xlnx,num-intr-inputs = <0x20>;
                          interrupt-parent = <&gic>;
                          interrupts = <0 89 4>;
                    };