15 Replies Latest reply on Mar 31, 2021 2:24 PM by bhfletcher

    Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1

    gjkunde

      Dear All,

       

      I cloned the 2020.1 branch for Avner hdf and petalinux and the master branch for bdf

       

      I run

      source /tools/Xilinx/Vivado/2020.1/settings64.sh

      ~/Avnet/petalinux/scripts$ ./make_ultra96v2.sh

       

       

      Verifying repositories ...

      Checking Environment (Xilinx tools sourced) ...

      Checking 'ultra96v2_oob/ULTRA96V2_2020_1' Vivado Project ...

      No built Vivado HW project ultra96v2_oob/ULTRA96V2_2020_1 found.

      Will build the hardware platform now.

      ****** Vivado v2020.1 (64-bit)

        **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020

        **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020

          ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

      source make_ultra96v2_oob.tcl -notrace

      *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

      *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

      *-                                                     -*

      *-        Welcome to the Avnet Project Builder         -*

      *-                                                     -*

      *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

      *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

      BDF path set to /home/gjkunde/Avnet/bdf

      +------------------+------------------------------------+

      | Setting          |     Configuration                  |

      +------------------+------------------------------------+

      | Board            |     ULTRA96V2                      |

      +------------------+------------------------------------+

      | Project          |     ultra96v2_oob                  |

      +------------------+------------------------------------+

      | SDK              |     no                             |

      +------------------+------------------------------------+

      | No Close Project |     yes                            |

      +------------------+------------------------------------+

      | Version override |     yes                            |

      +------------------+------------------------------------+

      | Device           |     zynqmp                         |

      +------------------+------------------------------------+

       

      and I get the following critical errors and warnings

       

      ***** Creating Block Design...

      Wrote  : </home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd>

      CRITICAL WARNING: [PSU-1]  Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.

       

      ***** Add defined IP blocks to Block Design...

      INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI

       

      WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

      CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.

      Please check your design and connect them as needed:

      /axi_intc_0/intr

       

       

       

      INFO: [BD 41-1662] The design 'ULTRA96V2.bd' is already validated. Therefore parameter propagation will not be re-run.

      WARNING: [BD 41-2180] Resetting the memory initialization file of </axi_bram_ctrl_0_bram> to default.

      CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.

      Please check your design and connect them as needed:

      /axi_intc_0/intr

       

       

      WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addra'(32) to pin: '/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected.

      WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addrb'(32) to pin: '/axi_bram_ctrl_0/bram_addr_b'(13) - Only lower order bits will be connected.

      VHDL Output written to : /home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/synth/ULTRA96V2.vhd

      WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addra'(32) to pin: '/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected.

      WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addrb'(32) to pin: '/axi_bram_ctrl_0/bram_addr_b'(13) - Only lower order bits will be connected.

      VHDL Output written to : /home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/sim/ULTRA96V2.vhd

      VHDL Output written to : /home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/hdl/ULTRA96V2_wrapper.vhd

       

       

      WARNING: [BD 41-2180] Resetting the memory initialization file of </axi_bram_ctrl_0_bram> to default.

      INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate

      INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate

      WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

      WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

      WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

      CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.

      Please check your design and connect them as needed:

      /axi_intc_0/intr

       

      Where am I going wrong here ?


      Thank you for helping, Gerd

        • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
          gjkunde

          Hello,

           

          I opened ./hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.xpr created with the scrip above,

          and run validate design, here is the output:

           

          validate_bd_design -force

          WARNING: [BD 41-2180] Resetting the memory initialization file of </axi_bram_ctrl_0_bram> to default.

          WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.

          INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16)

          WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

          WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16)

          CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.

          Please check your design and connect them as needed:

          /axi_intc_0/intr

           

          For the first warning they are:

           

           

          For they second warning they are:

           

          Would it be proper to set ARUSER_WIDTH to 16 ?

           

          Please advise, respectfully Gerd

              • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                gjkunde

                 

                The is apparently no input to the Interrupt Controller, is the proper solution to change the

                number of interrupts in the ip to zero ?

                 

                Please advise, respectfully Gerd

                  • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                    gjkunde

                     

                    This output of the AXI interrupt controller goes here, why does it have no inputs ?

                     

                    Please advise, Gerd

                      • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                        narrucmot

                        Hi Gerd,

                         

                        You can ignore the warnings during the Vivado build of this hw platform for the Ultra96-V2.  This hw platform has extra resources added to the programmable logic as "hooks" for subsequent Vitis and Vitis-AI development.  The Vitis tools will take care of adding the input to that axi_intc_0 interrupt controller.

                         

                        --Tom

                        1 of 1 people found this helpful
                          • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                            gjkunde

                            Thank you Tom,

                             

                            do you approve of:

                             

                             

                            That took care of the critical warning, also the  aw_user and ar_user width warning when away when

                            repackaged the IP.

                             

                            Respectfully Gerd

                              • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                gjkunde

                                I am still wondering about:

                                 

                                CRITICAL WARNING: [PSU-1]  Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.

                                  • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                    narrucmot

                                    Hi Gerd,

                                     

                                    We will investigate this DDR frequency issue and get back to you.

                                     

                                    --Tom

                                    • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                      narrucmot

                                      Hi Gerd,

                                       

                                      How are you building your Vivado project?  I have examined the Ultra96-V2 project I build using our TCL build scripted flow and I do not see the same critical warning.

                                       

                                      This is the process I use to build the Vivado hw platform (substitute for the Vivado version you are using):

                                      Avnet HDL git HOWTO (Vivado 2020.1 and earlier)

                                       

                                      This builds the hw platform that underlies the PetaLinux BSP that we post here on Element 14, so it is known-good.

                                       

                                      In your built Vivado project you should see the following settings for the DDR controller:

                                       

                                      Notice the "Requested Device Frequency" is 533 MHz and the "Actual Device Frequency" is 533.333313 MHz.  This is correct.  If you don't also see this then something is wrong in your build process.

                                       

                                      --Tom

                                        • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                          gjkunde

                                          $ git clone --branch 2020.1 https://github.com/Avnet/petalinux.git

                                          Cloning into 'petalinux'...

                                          fatal: unable to access 'https://github.com/Avnet/petalinux.git/': Failed to connect to github.com port 443: Connection refused

                                          gjkunde@Vitis:~/Avnet$ git clone --branch 2020.1 https://github.com/Avnet/petalinux.git

                                          Cloning into 'petalinux'...

                                          remote: Enumerating objects: 299, done.

                                          remote: Counting objects: 100% (299/299), done.

                                          remote: Compressing objects: 100% (141/141), done.

                                          remote: Total 2838 (delta 181), reused 235 (delta 122), pack-reused 2539

                                          Receiving objects: 100% (2838/2838), 9.29 MiB | 1.89 MiB/s, done.

                                          Resolving deltas: 100% (1511/1511), done.

                                          gjkunde@Vitis:~/Avnet$ git clone --branch 2020.1 https://github.com/Avnet/vitis.git

                                          Cloning into 'vitis'...

                                          remote: Enumerating objects: 182, done.

                                          remote: Counting objects: 100% (182/182), done.

                                          remote: Compressing objects: 100% (106/106), done.

                                          remote: Total 182 (delta 85), reused 146 (delta 54), pack-reused 0

                                          Receiving objects: 100% (182/182), 55.87 KiB | 2.23 MiB/s, done.

                                          Resolving deltas: 100% (85/85), done.

                                          gjkunde@Vitis:~/Avnet$ ls

                                          petalinux  vitis

                                          gjkunde@Vitis:~/Avnet$ git clone --branch 2020.1 https://github.com/Avnet/hdl.git

                                          Cloning into 'hdl'...

                                          remote: Enumerating objects: 65, done.

                                          remote: Counting objects: 100% (65/65), done.

                                          remote: Compressing objects: 100% (41/41), done.

                                          remote: Total 4402 (delta 26), reused 58 (delta 21), pack-reused 4337

                                          Receiving objects: 100% (4402/4402), 9.34 MiB | 1.93 MiB/s, done.

                                          Resolving deltas: 100% (2590/2590), done.

                                          gjkunde@Vitis:~/Avnet$ git https://github.com/Avnet/bdf.git

                                          git: 'https://github.com/Avnet/bdf.git' is not a git command. See 'git --help'.

                                          gjkunde@Vitis:~/Avnet$ git  clone https://github.com/Avnet/bdf.git

                                          Cloning into 'bdf'...

                                          remote: Enumerating objects: 30, done.

                                          remote: Counting objects: 100% (30/30), done.

                                          remote: Compressing objects: 100% (23/23), done.

                                          remote: Total 287 (delta 11), reused 26 (delta 7), pack-reused 257

                                          Receiving objects: 100% (287/287), 23.19 MiB | 1.94 MiB/s, done.

                                          Resolving deltas: 100% (108/108), done.

                                          gjkunde@Vitis:~/Avnet$ cd vitis

                                          gjkunde@Vitis:~/Avnet/vitis$ source /tools/Xilinx/Vitis/2020.1/settings64.sh

                                          gjkunde@Vitis:~/Avnet/vitis$ make ultra96v2_oob ‘step=xsa plnx sysroot pfm’

                                          /_\VNET Building Vitis Platform for Ultra96V2 Out Of Box

                                          make[1]: Entering directory '/home/gjkunde/Avnet/vitis/ultra96v2_oob'

                                          /_\VNET  Build Environment Configured for 2020_1 and

                                          /_\VNET  /home/gjkunde/Avnet/vitis/ultra96v2_oob with

                                          /_\VNET  Basename ultra96v2_oob

                                          /_\VNET  No Platform Specific file located, using ../mpsoc_linux.bif

                                          /_\VNET  No platform specific project_pfm.tcl, using ../project_pfm.tcl

                                          /_\VNET Making XSA

                                          make[2]: Entering directory '/home/gjkunde/Avnet/hdl/Scripts'

                                           

                                           

                                          ****** Vivado v2020.1 (64-bit)

                                            **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020

                                            **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020

                                              ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

                                           

                                           

                                          source make_ultra96v2_oob.tcl -notrace

                                           

                                           

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                          *-                                                     -*

                                          *-        Welcome to the Avnet Project Builder         -*

                                          *-                                                     -*

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                           

                                           

                                          BDF path set to /home/gjkunde/Avnet/bdf

                                           

                                           

                                           

                                           

                                           

                                           

                                          +------------------+------------------------------------+

                                          | Setting          |     Configuration                  |

                                          +------------------+------------------------------------+

                                          | Board            |     ULTRA96V2                      |

                                          +------------------+------------------------------------+

                                          | Project          |     ultra96v2_oob                  |

                                          +------------------+------------------------------------+

                                          | SDK              |     no                             |

                                          +------------------+------------------------------------+

                                          | No Close Project |     yes                            |

                                          +------------------+------------------------------------+

                                          | Version override |     yes                            |

                                          +------------------+------------------------------------+

                                          | Device           |     zynqmp                         |

                                          +------------------+------------------------------------+

                                           

                                           

                                           

                                           

                                           

                                           

                                          Overriding Version Check, Please Check the Design for Validity!

                                           

                                           

                                           

                                           

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                          Selected Board and Project as:

                                          ULTRA96V2 and ultra96v2_oob

                                          *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

                                           

                                           

                                           

                                           

                                          Not Requesting Tag

                                          Setting Up Project ultra96v2_oob...

                                           

                                           

                                          ***** Creating Vivado Project...

                                          ***** Assigning Vivado Project board_part Property to ultra96v2...

                                           

                                           

                                          ***** Generating IP...

                                           

                                           

                                          ***** Updating Vivado to include IP Folder

                                          INFO: [IP_Flow 19-234] Refreshing IP repositories

                                          INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gjkunde/Avnet/hdl/IP'.

                                          INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.1/data/ip'.

                                           

                                           

                                          ***** Creating Block Design...

                                          Wrote  : </home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd>

                                          CRITICAL WARNING: [PSU-1]  Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.

                                            • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                              bhfletcher

                                              Just wanted you to know that we are still looking at the problem. I did have some advice from a colleague who said he has seen strange errors when using the --branch flag. He suggested that you change "git clone --branch 2020.1 https://github.com/Avnet/petalinux.git" with 3 commands:

                                               

                                              1. git clone https://github.com/Avnet/petalinux.git
                                              2. cd petalinux
                                              3. git checkout 2020.1

                                               

                                              However, the strange error previously seen was not the DDR clock frequency being incorrect. We took one design that was cloned and built, opened it visually in Vivado, and all the settings were correct. We also reviewed the BDF, and those settings are also correct.

                                               

                                              Which Linux/VM version are you using?

                                               

                                              Thanks,

                                              Bryan

                                               

                                                • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                                  bhfletcher

                                                  Regarding this Critical Warning:

                                                  CRITICAL WARNING: [PSU-1]  Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.

                                                   

                                                  I am narrowing in on the cause. It appears to be a benign issue with Vivado and the default DDR memory that gets assigned to a fresh creation of the Zynq MPSoC IP in a block design. I was able to duplicate this warning in the Vivado GUI before the board preset was even applied. By default, Vivado selects a controller for DDR4. Unfortunately, the Actual Device Frequency gets set to 480 MHz. Apparently Vivado is performing some design rule check immediately after adding the IP but before you've had a chance to customize it. Since the DDR4 must run at a minimum of 500 MHz, you are issued the Critical Warning.

                                                   

                                                  But, not to worry! If I "Run Block Automation" and Apply the Board Preset, all of those previous settings get wiped away and so does the warning. Now you can see the same configuration set to LPDDR4 and 533.33 MHz.

                                                   

                                                  I think it is a mistake to issue the Critical Warning. I am discussing with Xilinx to see if this can be changed, but for now, you can ignore it.

                                                   

                                                  Bryan

                                                    • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                                      bhfletcher

                                                      Xilinx has now published an Answer Record that addresses this Critical Warning.

                                                      https://www.xilinx.com/support/answers/76233.html

                                                       

                                                      I'll leave my interpretation here as I think the AR is a bit misleading. Vivado has a bug when using I-grade parts. When you set up the project (whether that be for Ultra96-V2 or simply selecting an I-grade Xilinx ZU+ part), the Vivado default settings for the memory controller are invalid for the minimum 500 MHz frequency. You will immediately see the critical warning before you have even had a chance to do any sort of customization.

                                                       

                                                      This Critical Warning can be ignored. Move on with your design to either apply the Board Preset (which for Ultra96 will change the clock to 533 MHz) or customize the PS DDR Controller settings for your chip-level design to set the memory clock greater than 500 MHz.

                                                       

                                                      Xilinx also tells me that they have created a Change Request so that future versions of Vivado don't do the same thing and start you out with this Critical Warning with an I-grade device.

                                                       

                                                      Bryan

                                            • Re: Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1
                                              narrucmot

                                              As long as you are just planning on using this hw platform for use with PetaLinux thechange you made to add the constant tied to '0' on the axi_intc_0 input should be OK.  If you later want to use this hw platform with Vitis-AI it may cause problems.  That will take some experimentation.  I don't know what effect - if any - it will have.

                                               

                                              --Tom