1 Reply Latest reply on Apr 5, 2021 5:09 PM by bhfletcher

    LPDDR4 Initialize and Training Sequence




      We are trying to develop a validation platform for our lpddr4 devices using ultra96 board as a reference, and trying to understand the lpddr4 training sequences in ultra96.


      From the ug1085 ultrascale manual, there are some testing related to read operation which are read leveling, Read data bit deskew training and Read data eye training.

      And from Micron datasheets, there is read dq calibration.


      From DFI 4.0 spec, I guess that read data eye training is read dq calibration, then what are read leveling and read data bit de-skew? What does they do during training?



      Tan Zhi Hong