6 Replies Latest reply on May 17, 2021 10:09 AM by drozwood90

    Ultra96 v2 BSP hardware project




      I'm bharath and trying to understand the hardware implementation of a BSP project and hence I created project using 2020.1 BSP and Petalinux and opened the block diagram in Vivado. I don't understand the reason behind using so many system resets and different clocks used. Can anyone help me understand the logic behind this. Thank you in advance.

        • Re: Ultra96 v2 BSP hardware project

          Hi Bharath,


          I have reviewed what you have shown, and I agree that it doesn't make much sense. I expect this may be an artifact of something unexpected happening in the scripting. Let me get with the team and see if we can figure out why it is doing that.


          Thanks for bringing this to our attention!


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          • Re: Ultra96 v2 BSP hardware project

            Hi there,


            This is on purpose.  The Ultra96v2 is a highly flexible device that we use across many trainings, courses, reference designs, as well as for examples to customers.  The additional things you see there was a collaboration across our various teams to enable all of that in a coordinated way without everyone causing conflicts with each other's designs. 


            With the configuration you see there, that BASE design can be leveraged for general purpose PL work, Video (Dual Camera Mezzanine), Vitis AI, as well as Vitis HLS acceleration.  The available clocks and associated resets are required by the higher level platform needs.  For example, in Vitis HLS and Vitis AI, the tools use the processor reset and XLCONCAT blocks to communicate accelerated HLS to the PL and back from the PL to the PS.  While the logic does not have to be in place for these tools, the clocks and resets have to be part of the platform.


            If you would like to remove these, you can.  Anything we added as part of this should be under the "Vitis Additions" function in the build scripts for the 2020.1 branch.



            Keep in mind, for PL resources, anything that is not tied to an external pin and not used in some other way will be optimized out of the design anyway.



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