7 Replies Latest reply on Sep 9, 2021 12:05 PM by bhfletcher

    Netlength

    peter_clements

      Dear All, I have a question concerning the total netlength on the PicoZed boards as I am designing a carrier board for the PicoZed 7020. - There is a netlength file available in mils (https://www.avnet.com/wps/wcm/connect/onesite/ffb53454-fdcf-43af-9e60-fac05ef1f427/PicoZed+7010-7020+Net+Lenth+Rev+E.zip?MOD=AJPERES&CACHEID=ROOTWORKSPACE.Z18_NA5A1I41L0ICD0ABNDMDDG0000-ffb53454-fdcf-43af-9e60-fac05ef1f427-nIeby2m) in which the netlength only on the signal layers is indicated. - There is also a Carrier Design Guide PDF in which in Appendix A netlengths are available in mm. The netlength in the carrier design guide (by converting mils to mm) is not equal to the netlength of the signal layer file => and as it is bigger, does this means that in the PDF the indicated netlength = routed length + FPGA package length? Thank you

        • Re: Netlength
          bhfletcher

          I see the discrepancy too. Looks like the Net Length file is 60 mils longer than what is listed in the Carrier Design Guide. I'm fairly certain that the Net Length file is an auto-generated file straight out of Altium. I do not think that it includes the internal Xilinx package delays, as the delays will be different for 7Z010 vs 7Z020, so you wouldn't have a single 7010/20 table. The Carrier Design Guide's lengths are 60 mil shorter, which means it's not including anything extra.

           

          The contents in the Carrier Design Guide were manually entered into a document, which leaves the greatest room for error. I have sent a request to engineering asking about this discrepancy.

           

          Bryan

            • Re: Netlength
              peter_clements

              Dear Bryan, Thank you very much for taking into account my concern. Do you think it would be possible to obtain one single file where the picozeds netlength + FPGA package delays are packed together so that the board hardware persons like me without access to FPGA tools, do not need to do the extra effort of getting the package delays from somewhere and do the calculations ourselves? If not, would it be possible to make both files available ? Thank you very much for your understanding, Peter

                • Re: Netlength
                  bhfletcher

                  Hi Peter,

                   

                  PicoZed_7010_7020_RevE_NetLengths.xlsx

                   

                  It's not finished yet, but it has the PCB net lengths and the package delays for both 7z010 and 7z020 in the same spreadsheet. I need to find an easy way to map the PCB net names to the site names in the Xilinx package delays. I'll try to figure out a way to automate the PCB Length + Package Delay.

                   

                  Bryan

                    • Re: Netlength
                      peter_clements

                      Hi Bryan, I suppose the formula - in it's most basic form - is V=C/sqrt(Er) with C the speed of light and Er depends on the used material. This does not take into account any track width, height to ref layer etc, but should already give an approximation - do you agree ? Peter

                        • Re: Netlength
                          bhfletcher

                          I personally don't use those formulas, but they sound right . PCB manufacturers will give you the PCB flight time based on your material, copper weight, thickness, etc. A board that I analyzed in the past had the following characteristics (given to me by the PCB manufacturer):

                           

                           

                          I found this useful article on LinkedIn

                          https://www.linkedin.com/pulse/signal-speed-propagation-delay-pcb-transmission-line-amit-bahl/

                           

                          Knowing that Isola 370HR is a type of FR4 with Er = 4.0, my parameters above are very close to what the write describes in that article with microstrip (exterior layer) Tpd = 145 ps/in and stripline (interior layer) Tpd = 170 ps/in.

                           

                          For the very best numbers, consult your PCB manufacturer with the specific parameters of how you intend to build your board. If your goal is approximating, then the numbers above may be used.

                           

                          Bryan

                            • Re: Netlength
                              peter_clements

                              Hi Bryan, thanks for the answer - but the question is about the picozed hardware and how to account for the flight time on the FPGA instead of the hardware I'm building... Please read through the message above - have you updated the excel file? Thank you

                                • Re: Netlength
                                  bhfletcher

                                  Sorry it wasn't more clear. Those numbers above were for MicroZed, and PicoZed was identical in material and technology to MicroZed, so the numbers are the same. Therefore, for PicoZed I would use 170 ps/in for stripline and 136 ps/in for microstrip.

                                   

                                  I have not updated the Excel file yet to do the mapping. With Xilinx Adapt going on this week, my schedule has been quite busy.

                                  Bryan