4 Replies Latest reply on Sep 2, 2021 11:40 AM by genebren

    FPGA: trigger on both flanks of a clock to toggle output

    Jan Cumps

      I tried to take a naïve approach to (if needed) toggle an output pin either on the rising or falling edge of  clock signal.

      Line 17 below:

       

      entity variable_clock is
          Port ( 
            clk_i    : in  STD_LOGIC;
            resetn_i : in  STD_LOGIC;
            ticks_i  : in  STD_LOGIC_VECTOR (7 downto 0);
            clk_o    : out STD_LOGIC
          );
      end variable_clock;
      
      architecture Behavioral of variable_clock is
        signal counter_s: natural range 0 to 2**ticks_i'length-1 := 0;
        signal clk_out_s: STD_LOGIC := '0';
      begin
      
      process (clk_i, resetn_i)
      begin
        if rising_edge(clk_i) then
          if resetn_i = '0' then
            counter_s <= 0;
            clk_out_s <= '0';
          else
            if counter_s >= unsigned(ticks_i) then -- >= because the value can change
              counter_s <= 0;
              clk_out_s <= not clk_out_s;
            else
              counter_s <= counter_s + 1;
            end if;
            clk_o <= clk_out_s;
          end if;
        end if;
      end process;
      
      end Behavioral;
      

       

       

      This synthesises without errors, but the output is identical when I use

        if rising_edge(clk_i) then
      

      or

        if (rising_edge(clk_i) or falling_edge(clk_i)) then
      

      Not double speed when using both edges, as the naïve me would expect.

       

      Internet has many opinions and warnings on this subject - both for simulation and synthesis. Your thoughts?

        • Re: FPGA: trigger on both flanks of a clock to toggle output
          michaelkellett

          I've never tried this so all suggestions are theory only !

           

          Don't expect it to be easy to fool the tools into allowing this - FPGAs do not expect double data rate stuff internally.

          VHDL and simulation won't help you much - VHDL can do it easily - it's the synthesiser that chokes.

           

          Simple way - use a pll and double the clock speed

           

          But you are using a big fat and powerful Xilinx chip - its has DDR hardware on it's outputs.

          So you should be able to clock 2 bits in and get single double rate bits out.

          This will require a really good poke into the FPGA output hardware.

          There will be Xilinx examples you can look at.

           

          In fact - you may be able to go much further.

          For high speed serial ports for SERDES many FPGAs have "gearboxes" - which will take an 8 bit input at clock Q and output a bit stream at

          8 x Q. (Often support other ratios too)

           

          MK

          2 of 2 people found this helpful
            • Re: FPGA: trigger on both flanks of a clock to toggle output
              Jan Cumps

              ... Simple way - use a pll and double the clock speed

              Yes, I have that option. I also have headroom to up the input clock.

              But you are using a big fat and powerful Xilinx chip - its has DDR hardware on it's outputs.

              So you should be able to clock 2 bits in and get single double rate bits out.

              This will require a really good poke into the FPGA output hardware.

              There will be Xilinx examples you can look at.

               

              In fact - you may be able to go much further.

              For high speed serial ports for SERDES many FPGAs have "gearboxes" - which will take an 8 bit input at clock Q and output a bit stream at

              8 x Q. (Often support other ratios too)

               

              MK

              on the to-do and to-learn.

            • Re: FPGA: trigger on both flanks of a clock to toggle output
              wolfgangfriedrich

              I always try to remind myself that the

              if rising_edge ()

              statement is a special case as it does get synthesized into the clock input of a flip-flop instead of some logic gates/lookup tables. Putting more conditions into that if clause, especially the falling_edge() function would make the synthesizer throw up in some form or another as there is no easy hardware equivalent to implement that. I would hope that there would be at least some warnings from the tool, that some statements get ignored.

              - W.

              1 of 1 people found this helpful
              • Re: FPGA: trigger on both flanks of a clock to toggle output
                genebren

                Jan,

                 

                I remember that some Xilinx parts (XC9500 and CoolRunner CPLD) use to have DUALEdge or Cool_Clock logic built in.  They used special attributes to enable this feature into the synthesis process.

                 

                Here is a couple of wild approach to synthesize the same sort of thing with a little creativity and hand-waving (all credit to the previous posters):

                and

                Grant, years ago I published a reliable clock doubler circuit, part of the "six easy pieces" that seem to be lost.
                In words: Run your 10 MHz clock through a 2-input XOR. Generate a toggling flip-flop by feeding Q back through an
                inverting LUT to the D input. Route the signal driving D also to the second XOR input. Use the XOR output to clock
                the flip-flop, and also use it as your 20 MHz clock.  Disadvantage: If your 10 MHz doesn't have 50/50 duty cycle,
                your 20 MHz will have frequency modulation. And the High (or Low depending on XOR or XNOR) time of your 20 MHz clock
                will be short but you can lengthen it by adding delay to the Q- to-D path. Anyhow, it's self-adaptive to the device
                speed. Use this trick only when no PLL or DLL is available. Peter Alfke

                Both of these approaches should work and pass through synthesis as they both use combinatorial logic to blend the clocks.

                 

                Best of luck!

                Gene