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I see you have also found the Xilinx Community Forums, which is also a great place to ask. For cross-reference, here is your other post:
I'm not an R5 expert, but there is some good information about the various power domains which explains how you can run them independently of one another. These might be helpful reading for you.
Thanks for the response!
The documents you provided were very useful!
I have a few questions regarding the real-time cores (Cortex R5F) on the UltraScale+ EV:)
- Can the real-time cores run independently from the rest of the SoC?
- Do the real-time cores can have access to the SD card and CAN peripherals?
- Can the real-time cores interface with custom IPs on the FPGA? And are there any speed limitations compared to the APUs interface with the FPGA?
The main reason for using the R5-F cores is an attempt to conserve power in the system. The hope is to turn off the APUs and let the real-time cores perform some data movement tasks via the CAN bus (from an SD card). Would moving these operations over on the real-time cores, and shutting down the APUs, etc. conserve power?